Taiwan Semiconductor Manufacturing Company (TSMC) is stepping back from the most expensive path in chipmaking.
Instead of adopting the next generation of lithography machines, the company is choosing to extend the life of its current tools.
The decision reflects a broader shift across the semiconductor industry, where the cost of progress is becoming as important as the progress itself.
Cost Pressure Is Reshaping the Roadmap
TSMC introduced two new technologies. A13, expected near the end of the decade, targets high-performance AI systems. N2U is designed as a more cost-efficient alternative for consumer devices and mid-range computing.
Rather than moving to advanced high-NA EUV systems from ASML, TSMC plans to keep scaling using its existing EUV infrastructure. Each high-NA system is estimated to cost around $400 million, effectively doubling capital intensity at a time when chipmakers are already under pressure to control spending.
The largest AI players are now committing tens of billions of dollars annually to infrastructure, with companies like Nvidia at the center of that demand cycle.
TSMC’s approach is designed to keep that ecosystem economically sustainable.
Moore’s Law Is No Longer the Main Driver
The traditional model defined by Moore’s Law is no longer delivering the same returns.
As Jensen Huang and others have pointed out, shrinking transistors alone cannot maintain the pace of performance gains.
TSMC is responding by shifting where those gains come from.
Instead of focusing purely on node scaling, the company is redistributing innovation across packaging, interconnects, and system architecture.
The Center of Innovation Moves to Packaging
The most significant change is happening outside the transistor.
TSMC expects that by 2028 it will be able to combine up to 10 compute dies with 20 stacks of high-bandwidth memory into a single system. This is a structural shift in how chips are designed.
Performance is no longer defined by a single piece of silicon. It is defined by how multiple components operate together.
For companies like Apple and Google, this model offers a way to scale performance without relying on increasingly expensive fabrication steps.
In the AI sector, it may be the only viable path forward.
A Split Strategy Across the Industry
Not every major player is taking the same route.
Intel is investing heavily in next-generation lithography, betting that process leadership will still define competitiveness. Samsung Electronics is attempting to balance both advanced node development and packaging innovation.
TSMC’s strategy is different. It prioritizes economic efficiency and system-level performance over aggressive investment in new manufacturing equipment.
This divergence is likely to shape the competitive landscape over the next decade.
The New Constraints: Heat, Materials, and Scale
As chips become larger and more complex, new limits are emerging.
Thermal management is becoming a central challenge. AI processors already operate at high power densities, and multi-die systems intensify that problem.
Material stress is another issue. Different components expand at different rates under heat, increasing the risk of warping and structural damage in large chip packages.
These constraints are not theoretical. They are already affecting advanced processors in production.
The bottleneck is shifting from physics to engineering.
Conclusion
If TSMC’s strategy works, it could slow the rise in AI infrastructure costs at a critical moment. That would have direct implications for cloud providers, model developers, and any company relying on large-scale compute.
At the same time, it reinforces TSMC’s position at the center of the global chip supply chain.